K4S510732C cmos sdram rev. 0.1 sept.2001 stacked 512mbit sdram 16m x 8bit x 4 banks synchronous dram lvttl revision 0.1 sept. 2001 * samsung electronics reserves the right to change products or specification without
K4S510732C cmos sdram rev. 0.1 sept.2001 revision 0.0 (mar., 2001) revision 0.1 (sep., 2001) ? corrected typo. ? redefined idd1 & idd4 in dc characteristics ? changed the notes in operating ac parameter. < before > 5. for 1h/1l, trdl=1clk and tdal=1clk+trp is also supported . samsung recommends trdl=2clk and tdal=2clk + trp. < after > 5.in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp.
K4S510732C cmos sdram rev. 0.1 sept.2001 the K4S510732C is 536,870,912 bits synchronous high data rate dynamic ram organized as 4 x 16,777,216 words by 8 bits, fabri- cated with samsung ' s high performance cmos technology. syn- chronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system appli- cations. ? jedec standard 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation ? dqm for masking ? auto & self refresh ? 64ms refresh period (8k cycle) general description features functional block diagram 16m x 8bit x 4 banks synchronous dram 32mx8 32mx8 a0~a12,ba0,ba1 dq0 ~ dq7 clk,cas,ras /we,dqm /cs1,cke1 /cs0,cke0 * samsung electronics reserves the right to change products or specification without notice. staktek?s stacking technology is samsung?s stacking technology of choice. ordering information part no. max freq. interface package K4S510732C-tc/l7c 133mhz(cl=2) lvttl 54pin tsop(ii) K4S510732C-tc/l75 133mhz(cl=3) K4S510732C-tc/l1h 100mhz(cl=2) K4S510732C-tc/l1l 100mhz(cl=3)
K4S510732C cmos sdram rev. 0.1 sept.2001 v dd dq0 v ddq n.c dq1 v ssq n.c dq2 v ddq n.c dq3 v ssq n.c v dd cs1 we cas ras cs0 ba0 ba1 a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 pin configuration (top view) v ss dq7 v ssq n.c dq6 v ddq n.c dq5 v ssq n.c dq4 v ddq n.c v ss cke1 dqm clk cke0 a12 a11 a9 a8 a7 a6 a5 a4 v ss 54pin tsop (ii) (400mil x 875mil) (0.8 mm pin pitch) pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs0~1 chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke0~1 clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a 0 ~ a 12 address row/column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 12 , column address : ca 0 ~ ca 9 ba 0 ~ ba 1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas, we active. dqm data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. dq 0 ~ 7 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity.
K4S510732C cmos sdram rev. 0.1 sept.2001 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes : capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref =1.4v 200 mv) pin symbol min max unit note clock c clk 5.0 9.0 pf ras, cas, we, dqm c in 5.0 10.0 pf address c add 5.0 10.0 pf cs#, cke# ccs 2.5 6.5 pf dq 0 ~ dq 8 c out 8.0 14.0 pf
K4S510732C cmos sdram rev. 0.1 sept.2001 dc characteristics 1. measured with outputs open. 2. refresh period is 64ms. 3. K4S510732C-tc** 4. K4S510732C-tl** 5. unless otherwise noticed, input swing level is cmos(v ih /v il =v ddq /v ssq ). notes : (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note -7c -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 120 110 110 110 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 4 ma i cc2 ps cke & clk v il (max), t cc = 4 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 40 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 20 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 8 ma i cc3 ps cke & clk v il (max), t cc = 8 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 50 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 35 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated. t ccd = 2clks 140 140 130 130 ma 1 refresh current i cc5 t rc 3 t rc (min) 240 220 210 210 ma 2 self refresh current i cc6 cke 0.2v c 6 ma 3 l 3 ma 4
K4S510732C cmos sdram rev. 0.1 sept.2001 ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w outpu t 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp. notes : (ac operating conditions unless otherwise noted) parameter symbol version unit note -7c -75 -1h -1l row active to row active delay t rrd (min) 15 15 20 20 ns 1 ras to cas delay t rcd (min) 15 20 20 20 ns 1 row precharge time t rp (min) 15 20 20 20 ns 1 row active time t ras (min) 45 45 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 60 65 70 70 ns 1 last data in to row precharge t rdl (min) 2 clk 2, 5 last data in to active delay t dal (min) 2 clk + trp - 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1
K4S510732C cmos sdram rev. 0.1 sept.2001 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -7c -75 -1h -1l unit note min max min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 7.5 10 10 12 clk to valid output delay cas latency=3 t sac 5.4 5.4 6 6 ns 1,2 cas latency=2 5.4 6 6 7 output data hold time cas latency=3 t oh 3 3 3 3 ns 2 cas latency=2 3 3 3 3 clk high pulse width t ch 2.5 2.5 3 3 ns 3 clk low pulse width t cl 2.5 2.5 3 3 ns 3 input setup time t ss 1.5 1.5 2 2 ns 3 input hold time t sh 0.8 0.8 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 5.4 6 6 ns cas latency=2 5.4 6 6 7
K4S510732C cmos sdram rev. 0.1 sept.2001 simplified truth table (v=valid, x=don ' t care, h=logic high) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 12, a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes :
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